General Purpose Processors or Digital Signal Processors (DSP) generally require two operands for each processor cycle in order to utilize the processor efficiently. This is, in particular, mandatory due to the heavy processing load demanded in a typical signal processing task for which the digital signal processor is dedicated.
Conventionally, this requirement is addressed by allocating two distinct memory banks: one of which stores the data corresponding to the first operand, the other storing the data corresponding to the second operand. Consequently, two operands may be accessed simultaneously and transferred to a multiplier and/or an arithmetic logic unit (ALU) in order to be processed. The separate memory banks may be mapped at the same addresses, each having its own respective data addressing unit or, as is more commonly done, each of the banks may be mapped at a specified memory address.
Examples of such an approach may be found, for example, in the Texas Instrument TMS32025 User Guide and in the Motorola DSP56000 User Guide. Similarly, "Programmable DSP Architectures: Part I" by Edward A. Lee, IEEE ASSP Magazine, December 1988 provides a solution to the problem of simultaneous addressing of two memory locations using respective memory banks. Whilst such a solution serves as an effective arrangement for simultaneous addressing of two operands, it implies that the programmer must split his database into two pans. This may cause swapping of data between the two banks which increases the length of both the execution time and of the code. The resultant overhead in time and resources is clearly unsatisfactory in the signal processing real time environment in which tremendous effort is invested in the reduction of operating time.
It is known to use a dual port memory in order to obtain the desired memory bank mapping which will serve for efficient storage of both the two operand scheme instruction and a single operand scheme instruction. Thus, there is described in the Motorola DSP 56116 User Guide a device which may be accessed at two different addresses in the same cycle, whereby it is possible to access two operands simultaneously. Alternatively, only a single address may be accessed which is useful for the one operand access mode.
Whilst the dual port memory is the perfect solution from the architectural point of view, the dual port memory cell is much bigger than the previous single port memory cell and therefore, requires larger dies for its manufacture which are considerably more expensive, and therefore commercially unattractive for applications at the low end of the market.
For overcoming the contradictory requirements of a memory arrangement which serves equally well for accessing single operand instructions from a specified memory bank or dual operand instructions from either the same or different memory banks, two single port memory banks may be arranged so as to form a continuous address base. Thus, for example, two memory banks, each having a capacity of 512 bytes, may be mapped respectively at the address space of 0 to 511 and 512 to 1023, so as to produce a continuous address space. In operation, whenever it is desired to work in the two operand access mode, each memory bank is addressed in order to achieve the corresponding operand.
On the other hand, if the single operand mode be desired, then two alternative procedures must be considered. In the case where the data block which stores the first operand occupies less than 512 bytes, then the data may be stored in its entirety in only one of the memory banks or may be split, as required, between both memory banks. Alternatively, if the data block occupies more than 512 bytes, then there is no choice in the matter: the data must be split between both memory banks. The continuous memory characteristic ensures that if the address pointer is set to address 511 and the next operand is to be fetched, the pointer will be incremented so as to point to the address 512. Logic is provided to adjust the address 512 so as to point to the first byte of the second memory bank, whereby no overhead operations are required, this being an essential condition for the real time environment in which the digital signal processor is embedded.
By means of such an approach, the above-mentioned drawbacks are eliminated, there being provided an arrangement comprising two banks, each being a single port memory which enables both two operand and one operand mode of operation, whereby the commercial requirements are also met.
This notwithstanding, such an arrangement still fails to meet additional requirement: namely, the expansion of each memory bank. Thus, consider the situation in which it is desired to expand each of the memory banks from 512 bytes to 1 Kbyte. In such case, the 512 byte module is removed and replaced by a 1 Kbyte module. The same holds true for the second memory bank. Such an approach has two inherent drawbacks. First, it involves modifications to the hardware which in turn require the logic design to be reconfigured. Secondly, it gives rise to software incompatibility whereby code which was programmed before modification to the hardware was effected is no longer compatible with the new memory mapping. Thus, if the software points to an address corresponding to 520th byte, this would originally have pointed to a memory location in the second module. However, with the expanded memory, it will now need to point to a memory location in the expanded first module and will thus require modification to the software. The requirement to update all software on expanding the DSP's capacity is clearly undesirable.
It is therefore the object of the present invention to provide a memory arrangement scheme which will serve both for single and dual operand instruction types as the case may be, by utilizing a single port memory and, at the same time, to meet the additional requirement of flexible memory expansion and contraction by simply replacing the module, whilst retaining the continuous address space characteristic.